Tutorials



Silicon Lifecycle Management: Trends, Challenges and Solutions


  • Yervant Zorian
    • Chief Architect and Fellow, Synopsys Inc.

  • Date: August 24, 2022 (Wednesday)
  • Time: 13:30 - 16:30 (UTC+8)
  • Venue: Pegasus 室宿廳, 2F

Abstract:

Recent advances in automotive SOCs, artificial intelligence accelerators, and high-performance computing engines in data centers have led to an explosion in the adoption of emerging technology nodes and 3DIC/chiplet packages. This tutorial will present today’s trends and discuss on the resiliency challenges for such emerging SOCs. It will then focus on optimizing the SOC health using advanced solutions typically utilized for managing the different silicon lifecycle stages: from silicon debug in early bring up stage to shorten the time-to-volume; to self-test and repair during volume production stage, in order to improve quality and yield; to power-on self-test in the field stage to address aging challenges; to periodic checking in-system to improve functional safety; and finally to fault tolerance and error correction during mission mode to address a range of transient errors. All of the above optimizations are materialized by on-chip and/or off-chip data analytics.


Biography:

Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.

Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science.

He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.





Device-Aware-Test for Emerging Memories: The means to win the war against unmodeled faults

  • Said Hamdioui
    • Chair Professor on Dependable and Emerging Computer Technologies, Head of the Quantum and Computer Engineering department, Head of the Computer Engineering Laboratory (CE-Lab), Delft University of Technology
  • Date: August 24, 2022 (Wednesday)
  • Time: 13:30 - 16:30 (UTC+8)
  • Venue: Virgo 角宿廳, 2F

Abstract:

This tutorial discusses conventional memory testing approach and applies it to two emerging memory technologies STT-MRAMs and RRAMs. Thereafter, it introduces Device-Aware Test (DAT) and demonstrates it based on two industrial memory designs: STT-MRAMs and RRAMs.

DAT is a new test approach that goes beyond Cell-Aware Test; it does not assume that a defect in a device can be modeled electrically as a linear resistor (as the state-of-the-art approach suggests), but it rather incorporates the impact of the physical defect into the technology parameters of the device and thereafter in its electrical parameters. Once the defective electrical model is defined, a systematic fault analysis is performed to derive appropriate fault models and subsequently test solutions. Industrial case studies for STTMRAM and RRAM show that DAT sensitizes realistic faults as well as new unique defects and faults that can never be caught with the traditional approach.


Biography:

Said Hamdioui has presented many tutorials about memory testing (as part of TTTC TTEP) in the past; e.g., ITC, ITC-India, ETS and DATE. In addition, Hamdioui has been giving tutorials/consultancy on memory testing and reliability at worldwide leading semiconductor companies in Europe, USA and Asia.

Hamdioui is currently Chair Professor on Dependable and Emerging Computer Technologies, Head of the Quantum and Computer Engineering department, and also serving as Head of the Computer Engineering Laboratory (CE-Lab) of the Delft University of Technology, the Netherlands. He is also co-founder and CEO of Cognitive-IC, a start-up focusing on hardware dependability solutions and consultancy.

Hamdioui received the MSEE and PhD degrees (both with honors) from TUDelft. Prior to joining TUDelft as a professor, Hamdioui worked for Intel Corporation (Califorina, USA), Philips Semiconductors R&D (Crolles, France) and Philips/ NXP Semiconductors (Nijmegen, The Netherlands). His research focuses on two domains: emerging technologies and computing paradigms (including memristors,in-memory-computing, neuromorphic computing, low power HW architecture for edge AI, etc.), and hardware de-pendability (including Testability, Reliability, Hardware Security).







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Industrial Technology Research Institute
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