Keynote Speeches

Machine Learning-Based Weak Die Screening

  • Cheng-Wen Wu
    • Distinguished Chair Professor, Dept. EE, NTHU
    • SVP & Chief Technology Expert, ITRI
    • Chair Professor, Miin Wu School of Computing, NCKU

  • Date: August 25, 2022 (Thursday)
  • Time: 09:00 - 09:50 (UTC+8)
  • Venue: Jadeite 翡翠廳, 3F


It is always a challenging yet critical task to guarantee the quality and reliability of semiconductor products, given the fast advancing technologies in devices, circuits, wafer process, packaging, etc. On the other hand, we have noticed that the data driven prediction based on machine learning (ML) has provided a potential alternative to some conventional test methods, which can help improving product quality and reliability. In this talk, I will introduce a few ML-based screening methods for weak and bad dies, including integrated passive devices and advanced integrated circuits. We also show that feature selection in ML is very important in its accuracy and efficiency, which requires domain knowledge from test engineers and even designers.


CHENG-WEN WU received the BSEE degree from National Taiwan University, Taipei, Taiwan, in 1981, and the MS and PhD degrees in ECE from the University of California, Santa Barbara (UCSB), in 1985 and 1987, respectively. Since 1988, he has been with the Department of EE, National Tsing Hua University (NTHU), Hsinchu, Taiwan, where he is currently a Distinguished Chair Professor. He had served at NTHU as the Chair of EE Department, Director of IC Design Technology Center, Dean of the College of EECS, and Senior Vice President for Research. He took a leave from NTHU between Aug. 2019 and July 2021, serving as an Executive Vice President for National Cheng Kung University (NCKU). Since July 2020, he has been jointly appointed by ITRI, currently serving as the Senior Vice President and the Chief Technology Expert.

Dr. Wu received three Distinguished Research Awards from National Science Council, two Industrial Collaboration Awards from the Ministry of Education (MOE), the Academic Award from MOE, the Continuous Service Award and Outstanding Contribution Award from the IEEE Computer Society, the Distinguished Industrial Collaboration Award from NTHU, the National Invention Award (Silver Medal) from Ministry of Economic Affairs (MOEA), the TECO Award, the National Chair Professorship from MOE, the EE Medal from CIEE, the ATS 25th Anniversary Most Contribution Author Award and Most Influential Paper Award from TTTC, IEEE Computer Society, the Distinguished Achievement Award from the Phi Tau Phi Scholastic Honor Society of the ROC, the Distinguished Research Award of the Pan Wen Yuan Foundation, and the Industry Contribution Award of SEMI. His research interests include design and test of VLSI circuits and systems, semiconductor memory test and repair, and symbiotic neuromorphic computing. He is a life member of the CIEE, a life member of Taiwan IC Design Society, a Fellow of the ROC Technology Management Society, and a Fellow of the IEEE.

Toward Correct Understanding and Characterization of Cosmic ray-induced Soft Errors

  • Masanori Hashimoto
    • Professor, Kyoto University

  • Date: August 25, 2022 (Thursday)
  • Time: 10:10 - 11:00 (UTC+8)
  • Venue: Jadeite 翡翠廳, 3F


Soft error in integrated systems originating cosmic ray is a serious concern for reliability demanding applications, such as autonomous driving, supercomputer, and the public transportation system. Also, as the number of electronic devices increases, consumer electronics may require higher reliability than ever. On the other hand, device miniaturization and lower voltage operation degrade the immunity of VLSI, and then soft error countermeasures will be demanded in more and more products. This talk discusses soft error in the terrestrial environment focusing on the impact on society, technology trends, characterization methods, and countermeasures.


Masanori Hashimoto received the B.E., M.E., and Ph.D. degrees in communications and computer engineering from Kyoto University, Kyoto, Japan, in 1997, 1999, and 2001, respectively. Now, he is a Professor in the Department of Communications and Computer Engineering, Kyoto University. His current research interests include VLSI design and CAD, especially design for reliability, soft error characterization, timing and power integrity analysis, reconfigurable computing, and low-power circuit design.

Challenges in Design and Test of Compute-in-Memory

  • Meng-Fan (Marvin) Chang
    • Director of Corporate Research, TSMC
    • Distinguished Professor, National Tsing Hua Univerity

  • Date: August 25, 2022 (Thursday)
  • Time: 11:00 - 11:50 (UTC+8)
  • Venue: Jadeite 翡翠廳, 3F


Compute-in-memory (CIM) is a promising candidate to breaking through the so-called memory wall bottleneck and improve the energy efficiency of AI edge devices. This talk outlines the background, trends, and challenges involved in the circuit designs of embedded CIM macros using SRAM, ReRAM, STT-MRAM and PCM devices. Beyond reviewing recent silicon-proven embedded volatile and nonvolatile CIM macros, this work also discuss the challenges in testing and reliable computing of CIM chips.


Meng-Fan Chang received an M.S. degree from The Pennsylvania State University, US and a Ph.D. from National Chiao Tung University, Taiwan. He is currently a Distinguished Professor at National Tsing Hua University (NTHU) and a Director of Corporate Research at TSMC. Prior to 2006, Dr. Chang worked in industry for over 10 years. This included the design of memory compilers (Mentor Graphics; 1996 - 1997) and the design of embedded SRAM and Flash macros (Design Service Division of TSMC; 1997 - 2001). In 2001 Dr. Chang co-founded IPLib in Taiwan, where he developed embedded SRAM and ROM compilers, Flash macros, and Flat-cell ROM chips until 2006. His research interests include circuit design for volatile and nonvolatile memory, ultra-low-voltage systems, 3D-memory, circuit-device interactions, spintronic circuits, memory-based security circuits, memristor logics for neuromorphic computing, and compute-in-memory for artificial intelligence.

Dr. Chang has been serving as an associate editor for IEEE JSSC, IEEE TVLSI, IEEE TCAS-I, and IEEE TCAD. He has also been serving on the Executive Committee for IEDM, as well as Subcommittee Chairs for ISSCC, IEDM, DAC, ISCAS, VLSI-DAT, and ASP-DAC. He was a Distinguished Lecturer for IEEE Solid-State Circuits Society (SSCS) and Circuits and Systems Society (CASS) as well as the Chair of the Nano-Giga technical committee of CASS, and an administrative committee (AdCom) member of the IEEE Nanotechnology Council. He has been serving as Program Director for the Micro-Electronics Program at the Ministry of Science and Technology of Taiwan government as well as Chair of the IEEE Taipei Section, Associate Executive Director for Taiwan’s National Program of Intelligent Electronics (NPIE), and NPIE bridge program. He has been the recipient of several prestigious national-level awards in Taiwan, including Outstanding Research Award of MOST-Taiwan, Outstanding Electrical Engineering Professor Award, Academia Sinica Junior Research Investigator Award, and Ta-You Wu Memorial Award. Dr. Chang is a Fellow of the IEEE.

A Cambrian Explosion in Electronic System Testing is Dead Ahead

  • Subhasish Mitra
    • Professor, Stanford University

  • Date: August 26, 2022 (Friday)
  • Time: 08:30 - 09:20 (UTC+8)
  • Venue: LEO 軒轅廳, 2F


Today's test technologies mostly serve 20th-century manufacturing needs of silicon CMOS chips. In this new decade, testing is going to change radically, driven by several factors: (a) Today's test methods cannot meet the levels of thoroughness demanded by today's (and future) systems --- from (self-driving) cars to the cloud. (b) Testing must grow beyond manufacturing defects to address robustness that end-users really care about: design bugs, reliability, and security. (c) Beyond-silicon NanoSystems create new testing challenges. These factors create golden opportunities for new "System-Driven" test approaches that address the above seemingly diverse problems at seemingly diverse scales. Testing will then become an essential 21st-century system feature rather than a cost burden defined by the constraints of 20th-century chip manufacturing.


Subhasish Mitra is Professor of Electrical Engineering and of Computer Science at Stanford University. He directs the Stanford Robust Systems Group, leads the Computation Focus Area of the Stanford SystemX Alliance, and is a member of the Wu Tsai Neurosciences Institute. His research ranges across Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences. Results from his research group have influenced almost every contemporary electronic system, and have inspired significant government and research initiatives in multiple countries. He has held several international academic appointments — the Carnot Chair of Excellence in NanoSystems at CEA-LETI in France, Invited Professor at EPFL in Switzerland, and Visiting Professor at the University of Tokyo in Japan. Prof. Mitra also has consulted for major technology companies including Cisco, Google, Intel, Samsung, and Xilinx. In the field of Robust Computing, he has created many key approaches for circuit failure prediction, on-line diagnostics, QED system validation, soft error resilience, and X-Compact test compression. Their adoption by industry is growing rapidly, in markets ranging from cloud computing to automotive systems. His X-Compact approach has proven essential for cost-effective manufacturing and high-quality testing of almost all 21st century systems, enabling billions of dollars in cost savings.

With his students and collaborators, he demonstrated the first carbon nanotube computer. They also demonstrated the first 3D NanoSystem with computation immersed in data storage. These received wide recognition: cover of NATURE, Research Highlight to the US Congress by the NSF, and highlight as "important scientific breakthrough" by global news organizations. Prof. Mitra's honors include the Harry H. Goode Memorial Award (by the IEEE Computer Society for outstanding contributions in the information processing field), Newton Technical Impact Award in EDA (test-of-time honor by ACM SIGDA and IEEE CEDA), the University Researcher Award (by the Semiconductor Industry Association and Semiconductor Research Corporation to recognize lifetime research contributions), the Intel Achievement Award (Intel’s highest honor), and the US Presidential Early Career Award. He and his students have published over 10 award-winning papers across 5 topic areas (technology, circuits, EDA, test, verification) at major venues including the Design Automation Conference, International Solid-State Circuits Conference, International Test Conference, Symposium on VLSI Technology, Symposium on VLSI Circuits, and Formal Methods in Computer-Aided Design. Stanford undergraduates have honored him several times "for being important to them." He is an ACM Fellow and an IEEE Fellow.

Going beyond Screening

  • Michael Campbell
    • Sr. Vice President in Qualcomm, USA

  • Date: August 26, 2022 (Friday)
  • Time: 09:20 - 10:10 (UTC+8)
  • Venue: LEO 軒轅廳, 2F


In the era of multi-billion transistor chips, the semiconductor market is heading toward a trillion dollars by 2030. On the road to the trillion-dollar market, the testing regimes from Pre-silicon EDA and in fabrication testing to Post-silicon Design validation wafer sort, final test, through SLT are all colliding in the boundless data space. This brings to light new market opportunities and disconnects.

What is driving the change to the 40+ year of process that historically brought the chip to market one well defined step at a time? What are potential solutions and areas of investigation for market convergence? Where will the disconnects potentially drive new businesses to evolve? What changes will this evolution of the Semiconductor industry bring? Are we ready to accept that change?


Michael Campbell is Senior Vice President of Engineering for QUALCOMM CDMA Technologies, responsible for QCT Product and Test, Test Automation, Failure Analysis and yield. Mike joined QCT in 1996 and since then Mike has led multiple teams including, FA, Quality, Design Automation, Yield optimization, Product Engineering, Test Engineering, and Foundry semiconductor analysis.

While at Qualcomm, Mike has helped bring up and drive the design office in Bangalore, Design and Test development center in Singapore and a development facility in Taiwan. In his current role, he is working to improve / stream all processes impacting TTM, new process node enablement, and revolutionize PTE tasks by driving machine learning as a 21st century requirement for all facets of PTE and Yield engineering work.

Prior to joining QUALCOMM, Mike was with other companies, including Mostek, INMOS and Honeywell. He holds a BSEE & CE from Clarkson University.

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