Advance Program


Note: Those papers with red star symbols "*" are the Best Paper Candidates.

[T1] Tutorial 1

Session Chair: Shi-Yu Huang, National Tsing Hua University
Date: Aug. 24, 2022 (Wednesday)
Time: 13:30 – 16:30
Room: Pegasus 室宿廳, 2F

ID Title / Authors / Affiliation
T1 Silicon Lifecycle Management: Trends, Challenges and Solutions
Yervant Zorian
Synopsys Inc.

[T2] Tutorial 2

Session Chair: Hung-Pin (Charles) Wen, National Yang Ming Chiao Tung University
Date: Aug. 24, 2022 (Wednesday)
Time: 13:30 – 16:30
Room: Virgo 角宿廳, 2F

ID Title / Authors / Affiliation
T2 Device-Aware-Test for Emerging Memories: The means to win the war against unmodeled faults
Said Hamdioui
Delft University of Technology

[O] Opening Ceremony

Session Chair: Soon-Jyh Chang, National Cheng Kung University
Date: Aug. 25, 2022 (Thursday)
Time: 08:40 – 09:00
Room: Jadeite 翡翠廳, 3F

[K1] Keynote 1

Session Chair: Soon-Jyh Chang, National Cheng Kung University
Date: Aug. 25, 2022 (Thursday)
Time: 09:00 – 09:50
Room: Jadeite 翡翠廳, 3F

ID Title / Authors / Affiliation
K1 Machine Learning-Based Weak Die Screening
Cheng-Wen Wu
National Tsing Hua University

[K2] Keynote 2

Session Chair: Hung-Pin (Charles) Wen, National Yang Ming Chiao Tung University
Date: Aug. 25, 2022 (Thursday)
Time: 10:10 – 11:00
Room: Jadeite 翡翠廳, 3F

ID Title / Authors / Affiliation
K2 Toward Correct Understanding and Characterization of Cosmic ray-induced Soft Errors
Masanori Hashimoto
Kyoto Universitya

[K3] Keynote 3

Session Chair: Jiun-Lang Huang, National Taiwan University
Date: Aug. 25, 2022 (Thursday)
Time: 11:00 – 11:50
Room: Jadeite 翡翠廳, 3F

ID Title / Authors / Affiliation
K3 Challenges in Design and Test of Compute-in-Memory
Meng-Fan (Marvin) Chang
TSMC

[A1] Regular Session 1: Memory and Test Structure

Session Chair: Hao-Chiao Hong, National Yang Ming Chiao Tung University
Date: Aug. 25, 2022 (Thursday)
Time: 13:30 – 14:45
Room: Pegasus 室宿廳, 2F

ID Title / Authors / Affiliation
*A1-1 Fault Resilience Techniques for Flash Memory of DNN Accelerators
Shyue-Kung Lu, Yu-Sheng Wu, Jin-Hua Hong1 , and Kohei Miyase2
National Taiwan University of Science and Technology
1National University of Kaohsiung
2Kyushu Institute of Technology
(Best Paper Candidate)
A1-2 Fault Modeling and Testing for RRAM-based Computing-In-Memories
Yu-Cheng Yang and Jin-Fu Li
National Central University
*A1-3 Diagnosing Transition Delay Faults under Scan-Based Logic Array
Duo-Yao Kang, Shiou-Ning Lin, and Kuen-Jong Lee
National Cheng Kung University
(Best Paper Candidate)

[B1] Special Session 1: Unlocking Value of Data from Silicon to System

Session Chair: Harry Chen, MediaTek Inc.
Date: Aug. 25, 2022 (Thursday)
Time: 13:30 – 14:45
Room: Virgo 角宿廳, 2F

ID Title / Authors / Affiliation
B1-1 Grow Productivity by Connecting the Worlds of Post- and Pre-Silicon Verification
Fred Pan
NI
B1-2 SOC health monitoring from production to the field with deep data analytics
Marc Hutner
proteanTecs
B1-3 Deep insights from fine-grain post-silicon profiling via existing DFT infrastructure
Harry H. Chen
MediaTek

[A2] Regular Session 2: Test Data Analysis

Session Chair: Tong-Yu Hsieh, National Cheng Kung University
Date: Aug. 25, 2022 (Thursday)
Time: 15:05 – 16:20
Room: Pegasus 室宿廳, 2F

ID Title / Authors / Affiliation
*A2-1 A Decision Tree-Based Screening Method for Improving Test Quality of Memory Chips
Ya-Chi Cheng1, Pai-Yu Tan2, Cheng-Wen Wu1,2, Ming-Der Shieh1, Chien-Hui Chuang3, and Gordon Liao3
1National Cheng Kung University
2National Tsing Hua University
3Taiwan Semiconductor Manufacturing Co., Ltd.
(Best Paper Candidate)
A2-2 Weak Die Screening by Feature Prioritized Random Forest for Improving Semiconductor Quality and Reliability
Shian-Yu Lin1, Pai-Yu Tan2, Cheng-Wen Wu1, 2, Ming-Der Shieh1, Chien-Hui Chuang3, and Gordon Liao3
1National Cheng Kung University
2National Tsing Hua University
3Taiwan Semiconductor Manufacturing Co., Ltd.
A2-3 Wafer Map Pattern Analytics Driven By Natural Language Queries
Yueling Zeng, Min Jian Yang, and Li-C Wang
University of California, Santa Barbara

[B2] Industry Session: Latest Technologies and Trends

Session Chair: Shi-Yu Huang, National Tsing Hua University
Date: Aug. 25, 2022 (Thursday)
Time: 15:05 – 16:20
Room: Virgo 角宿廳, 2F

ID Title / Authors / Affiliation
B2-1 Practical Aspects of IEEE 1838 3D IC DFT Implementation and Interconnect Test
Sagar Kumar*, Vivek Chickermane, and Rajesh Khurana
Cadence Design Systems
B2-2 Silicon Test & Analytics Throughout the Product Lifecycle
TP Tai
Synopsys
B2-3 Silicon Lifecycle Solution Scaling for Technology, Design and System
Wu Yang
Siemens EDA

[K4] Keynote 4

Session Chair: Chien-Mo (James) Li, National Taiwan University
Date: Aug. 26, 2022 (Friday)
Time: 08:30 – 09:20
Room: LEO 軒轅廳, 2F

ID Title / Authors / Affiliation
K4 A Cambrian Explosion in Electronic System Testing is Dead Ahead
Subhasish Mitra
Stanford University

[K5] Keynote 5

Session Chair: Jing-Jia Liou, National Tsing Hua University
Date: Aug. 26, 2022 (Friday)
Time: 09:20 – 10:10
Room: LEO 軒轅廳, 2F

ID Title / Authors / Affiliation
K5 Going beyond Screening
Michael Campbell
Qualcomm

[A3] Special Session 2: 3D IC for the Era of More Than Moore’s Law

Session Chair: Yang Wu, Siemens EDA
Date: Aug. 26, 2022 (Friday)
Time: 10:30 – 12:00
Room: LEO 軒轅廳, 2F

ID Title / Authors / Affiliation
A3-1 Industry Test Solutions for the 3D Era
Phil Nigh
Broadcom
A3-2 DFT and Testing Challenge for 2.5D and 3D IC
Xian Lu
MediaTek
A3-3 Challenges and Solutions for 3D FabricTM: A Foundry Perspective
Sandeep Kumar Goel
TSMC
A3-4 Making 3D DFT with IEEE 1838 work
Martin Keim
Siemens EDA

[A4] Regular Session 3: Logic Testing

Session Chair: Tsung-Chu Huang, National Changhua University of Education
Date: Aug. 26, 2022 (Friday)
Time: 13:30 – 14:45
Room: Pegasus 室宿廳, 2F

ID Title / Authors / Affiliation
A4-1 Timing-Critical Path Analysis in Circuit Designs Considering Aging with Signal Probability
Jiun-Cheng Tsai, Aaron C.-W. Liang, and Charles H.-P. Wen
National Yang Ming Chiao Tung University
A4-2 Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits
Taiki Utsunomiya1, Ryu Hoshino1, Kohei Miyase1, Shyue-Kung Lu2, Xiaoqing Wen1, and Seiji Kajihara1
1Kyushu Institute of Technology
2National Taiwan University of Science and Technology
A4-3 Test Response Compaction for Software-Based Self-Test
Jia-Ruei Liang, Ya-Ni Hsieh, and Jiun-Lang Huang
National Taiwan University

[B4] Invited Session: Testing and Reliability of Computing-In-Memories

Session Chair: Jin-Fu Li, National Central University
Date: Aug. 26, 2022 (Friday)
Time: 13:30 – 14:45
Room: Virgo 角宿廳, 2F

ID Title / Authors / Affiliation
B4-1 Testing and Reliability of Computing-In-Memories: Solutions and Challenges
Jin-Fu Li
National Central University
B4-2 Structured Test Development Approach for Computation-in-Memory Architectures
Moritz Fieback, Mottaqiallah Taouil, and Said Hamdioui
Delft University of Technology
B4-3 A Failure Analysis Framework of ReRAM In-Memory Logic Operations
L. Brackmann1, A. Jafari2, C. Bengel1, M. Mayahinia2, R. Waser1,3,4, D. Wouters1, S. Menzel3, and M. Tahoori2
1Institut fur Werkstoffe der Elektrotechnik II RWTH Aachen
2Karlsruhe Institute of Technology
3Peter Grunberg Institut (PGI-7) Forschungszentrum Julich
4Peter Grunberg Institut (PGI-10) Forschungszentrum Julich

[A5] Regular Session 4: Design for Security and Reliability

Session Chair: Hsin-Shu Chen, National Taiwan University
Date: Aug. 26, 2022 (Friday)
Time: 15:05 – 16:15
Room: Pegasus 室宿廳, 2F

ID Title / Authors / Affiliation
A5-1 Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS
Aibin Yan1, Shukai Song1, Jixiang Zhang1, Jie Cui1, Zhengfeng Huang2, Tianming Ni3, Xiaoqing Wen4, and Patrick Girard5
1Anhui University
2Hefei University of Technology
3Anhui Polytechnic University
4Kyushu Institute of Technology
5University of Montpellier / CNRS
A5-2 A Novel Dual Logic Locking Method to Prevent Counterfeit IP/IC
Aobo Cui, Dongrong Zhang, Qiang Ren, and Donglin Su
Beihang University
A5-3 A Physically Unclonable Function Embedded in a SAR ADC
Yi-Ying Chen and Soon-Jyh Chang
National Cheng Kung University

[B5] Regular Session 5: Error Tolerance

Session Chair: Shyue-Kung Lu, National Taiwan University of Science and Technology
Date: Aug. 26, 2022 (Friday)
Time: 15:05 – 15:55
Room: Virgo 角宿廳, 2F

ID Title / Authors / Affiliation
B5-1 An Improvement of the No-reference Test Scheme Based on False Edge Detection for Image Processing Application
Hideyuki Ichihara, Naruki Itoh, and Tomoo Inoue
Hiroshima City University
B5-2 Evaluating the impact of Permanent Faults in a GPU running a Deep Neural Network
Juan-David Guerrero-Balaguera1, Luigi Galasso1, Robert Limas Sierra2, Ernesto Sanchez1, and Matteo Sonza Reorda1
1Politecnico di Torino
2Universidad Pedagogica y Tecnologica de Colombia (UPTC)

[C] Closing

Date: Aug. 26, 2022 (Friday)
Time: 16:15 – 16:30
Room: Virgo 角宿廳, 2F




Supporters
Gold Sponsorship
Industrial Technology Research Institute
Cadence

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Siemens
Synopsys



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